1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device and more particularly, to an array substrate for a liquid crystal display (LCD) device and a manufacturing method of the same.
2. Discussion of the Related Art
In general, a liquid crystal display (LCD) device utilizes the optical anisotropy and birefringence properties of liquid crystal molecules to display images. The liquid crystal display (LCD) device usually has first and second substrates spaced apart from and opposing each other. The first and second substrates respectively have electrodes for forming an electric field between the electrodes. That is, if voltage is applied to the electrodes of the liquid crystal display (LCD) device, an electric field is formed between the electrodes and the electric field changes alignments of the liquid crystal molecules. The changed alignments of the liquid crystal molecules control a light transmittance through the liquid crystal and thus images can be displayed by controlling the light transmittance through the liquid crystal.
FIG. 1 is an exploded perspective view of a related art liquid crystal display (LCD) device. In FIG. 1, a liquid crystal display (LCD) device 11 has an upper substrate 5 having a black matrix 6, a color filter layer 8, and a common electrode 18 on the color filter layer 8, and a lower substrate 22 having a switching element T and a pixel electrode 17 at each pixel region P defined on the lower substrate 22. A liquid crystal layer 14 is interposed between the upper substrate 5 and the lower substrate 22.
Array lines are formed around the pixel region P. The lower substrate 22 may be commonly referred to as an array substrate. Thin film transistors T are arranged in a matrix form as the switching element, and are disposed crossing portions of gate and data lines 13 and 15. The gate and data lines 13 and 15 define the pixel region P by crossing each other, and in the pixel region P, the transparent pixel electrode 17 is formed. The pixel electrode 17 is formed of transparent conductive metal material such as indium tin oxide (ITO) that relatively reflects light well.
A storage capacitor C connected to the pixel electrode 17 in parallel is formed over the gate line 13. A portion of the gate line 13 serves as a first storage electrode and a metal layer 30 formed of the same material as source and drain electrodes serves as a second storage electrode. The metal layer 30 is connected to the pixel electrode 17, and receives signals of the pixel electrode 17.
The number of array lines and driving integrated circuits of the LCD device having the above structure increase as the size of the device increases or the resolution of the device increases.
To reduce the number of driving integrated circuits, a method for driving two pixels by using one data line and one gate line has been researched.
In this method, time variation is generated in two pixels commonly connected to one data line by switching a thin film transistor on and off, and thus sequential data signals are applied to the two pixels.
However, the method needs more thin film transistors at each pixel as compared with a general structure. This decreases an aperture ratio of the device. In addition, the numbers of thin film transistors are asymmetric in adjacent pixels with respect to the data line commonly contacted by the adjacent pixels.
FIG. 2 is a plan view showing an array substrate for a liquid crystal display device having a data line sharing structure according to a first embodiment of the related art.
As shown in FIG. 2, gate lines 31 are formed on a substrate 30 in a first direction and a data line 46 is formed in a second direction. The gate lines 31 and the data line 46 perpendicularly cross each other to define a first pixel region P1 and a second pixel region P2. Transparent pixel electrodes 52 and 54 are formed in the first and second pixel regions P1 and P2, respectively.
A driving thin film transistor (TFT) Ts is formed in each pixel region P1 and P2. A synchronization adjusting thin film transistor (TFT) Tc is formed in the first pixel region P1, and inputs signals from the driving TFT Ts to the pixel electrode 52. The synchronization adjusting TFT Tc can be formed in one of two pixel regions, which are referred to as an odd pixel region or an even pixel region, adjoining each other with respect to a particular data line 46.
The driving TFTs Ts formed in the adjacent pixel regions P1 and P2 are connected to the same data line 46. Different signals are transmitted through the data line 46. The synchronization adjusting TFT Tc is formed to sequentially transmit the different signals.
Each driving TFT Ts includes a gate electrode 32a, an active layer 38a, a source electrode 42a, and a drain electrode 44a. The synchronization adjusting TFT Tc includes a gate electrode 32b, an active layer 38b, a source electrode 42b, and a drain electrode 44b. 
A common line 36 is formed parallel to and spaced apart from the gate lines 31, and traverses the first and second pixel regions P1 and P2. A metal pattern 45 is formed over the common line 36 in each pixel region P1 and P2. The metal pattern 45 is connected to each pixel electrode 52 and 54. Thus, a storage capacitor Cst is formed in each pixel region P1 and P2. The common line 36 functions as a first electrode and the metal pattern 45 acts as a second electrode of the storage capacitor Cst.
In the pixel region P1 where the driving TFT Ts and the synchronization adjusting TFT Tc are formed, the driving TFT Ts and the synchronization adjusting TFT Tc are connected to adjacent gate lines 31, respectively, and thus are spaced apart from each other.
Accordingly, in the first pixel region P1, the first drain electrode 44a of the driving TFT Ts and the second source electrode 42b of the synchronization adjusting TFT Tc are connected to each other through a connection line 48.
Since the additional connection line 48 is formed, the aperture ratio of the pixel region containing the additional connection line 48 and synchronization adjusting TFT Tc is decreased.
FIGS. 3 and 4 show cross-sections of an array substrate for a liquid crystal display device according to the first embodiment of the related art. FIG. 3 is a cross-sectional view along the line III-III of FIG. 2 and FIG. 4 is a cross-sectional view along the line IV-IV of FIG. 2.
As shown in FIGS. 3 and 4, first and second pixel regions P1 and P2 are defined on a substrate 30. A driving TFT Ts is formed in each pixel region P1 and P2, and a synchronization adjusting TFT Tc is formed in the first pixel region P1. The synchronization adjusting TFT Tc is connected to the driving TFT Ts in the first pixel region P1. The driving TFT Ts and the synchronization adjusting TFT Tc are simultaneously formed through the same process.
More particularly, a gate electrode 32a for the driving TFT Ts and a gate electrode 32b for the synchronization adjusting TFT Tc are formed on the substrate 30. Although not shown in the figures, gate lines are formed of the same material in the same layer as the gate electrodes 32a and 32b. The gate lines are spaced apart from each other, and are connected to the gate electrodes 32a and 32b, respectively.
A gate insulating layer 33 is formed on the gate electrodes 32a and 32b, and active layers 38a and 38b and ohmic contact layers 40a and 40b are formed by sequentially depositing intrinsic amorphous silicon and impurity-doped amorphous silicon and then patterning these layers.
Source electrodes 42a and 42b and drain electrodes 44a and 44b are formed on the ohmic contact layers 40a and 40b. The source electrodes 42a and 42b are near by and spaced apart from the drain electrodes 44a and 44b, respectively. At the same time, a connection line 48 is formed to connect the drain electrode 44a of the driving TFT Ts with the source electrode 42b of the synchronization adjusting TFT Tc in the first pixel region P1.
Next, a passivation layer 50 is formed by depositing an inorganic insulating material such as silicon nitride (SiNx) and silicon oxide (SiO2) on an entire surface of the substrate 30 including the source electrodes 42a and 42b and the drain electrodes 44a and 44b of the driving TFT Ts and the synchronization adjusting TFT Tc thereon.
Pixel electrodes 52 and 54 are formed on the passivation layer 50 in respective pixel regions P1 and P2. The pixel electrode 52 of the first pixel region P1 is connected to the driving TFT Ts and the synchronization adjusting TFT Tc and the pixel electrode 54 of the second pixel region P2 is connected to the driving TFT Ts.
As stated above, the connection line 48 connecting the driving TFT Ts and the synchronization adjusting TFT Tc occupies a portion of the first pixel region P1 and thus both substantially reduces the aperture ratio of the LCD device and causes non-uniform brightness in adjacent pixels with respect to the data line 46. Thus, the quality of the images produced is lowered.
FIG. 5 is a plan view showing an array substrate for a liquid crystal display device according to a second embodiment of the related art. The array substrate of the second embodiment also has the above-mentioned problems.
As shown in FIG. 5, gate lines 61 are formed in a first direction on a substrate 60, and data lines 76 are formed in a second direction crossing the first direction. The gate lines 61 and the data lines 76 perpendicularly cross each other to define a plurality of pixel regions P.
In each pixel region P, a driving TFT Ts and a synchronization adjusting TFT Tc are formed. The driving TFT Ts includes a gate electrode 62a, an active layer 66a over the gate electrode 62a, and source and drain electrodes 70a and 72a spaced apart from each other over the active layer 66a. The synchronization adjusting TFT Tc includes a gate electrode 62b, an active layer 66b over the gate electrode 62b, and source and drain electrodes 70b and 72b spaced apart from each other over the active layer 66b. Additionally, a transparent pixel electrode 80 is formed in each pixel region P.
The drain electrode 72a of the driving TFT Ts is connected to the source electrode 70b of the synchronization adjusting TFT Tc through a connection line 74, and the drain electrode 72b of the synchronization adjusting TFT Tc is connected to the pixel electrode 80.
In this embodiment, adjacent pixel regions up and down in the context of the figure are commonly connected to a single gate line 61 and receive signals. Therefore, to sequentially apply the signals to the pixels, the driving TFT Ts and the synchronization adjusting TFT Tc are formed in one pixel region P. The driving TFT Ts and the synchronization adjusting TFT Tc in the same pixel region P are connected to different gate lines 61.
A common line CL is also formed in the pixel region P and is spaced apart from and parallel to the gate line 61.
A storage capacitor Cst is formed over the common line CL. A part of the common line CL functions as a first electrode and an extension part 75 extending from the drain electrode 72b of the synchronization adjusting TFT Tc acts as a second electrode of the storage capacitor Cst.
The aperture ratio of the LCD device according to this embodiment is also reduced due to the connection line 74 for connecting the driving TFT Ts and the synchronization adjusting TFT Tc.
FIGS. 6 and 7 show cross-sections of an array substrate for a liquid crystal display device according to the second embodiment of the related art. FIG. 6 is a cross-sectional view along the line VI-VI of FIG. 5 and FIG. 7 is a cross-sectional view along the line VII-VII of FIG. 5.
As shown in the figures, a driving TFT Ts and a synchronization adjusting TFT Tc are formed in each pixel region P, which is defined on a substrate 60.
A gate electrode 62a of the driving TFT Ts and a gate electrode 62b of the synchronization adjusting TFT Tc are formed on the transparent insulating substrate 60. A gate insulating layer 64 is formed on the gate electrodes 62a and 62b, and active layers 66a and 66b and ohmic contact layers 68a and 68b are formed on the gate insulating layer 64 by sequentially depositing amorphous silicon (a-Si:H) and doped amorphous silicon (n+ or p+ a-Si:H) and then patterning them.
Source electrodes 70a and 70b and drain electrodes 72a and 72b are formed on the ohmic contact layers 68a and 68b. The source electrodes 70a and 70b are spaced apart from the drain electrodes 72a and 72b, respectively. At the same time, a connection line 74 is formed to connect the drain electrode 72a of the driving TFT Ts with the source electrode 70b of the synchronization adjusting TFT Tc. A data line 76 is also formed of the same material as the source electrodes 70a and 70b and the drain electrodes 72a and 72b and is connected to the source electrode 70a of the driving TFT Ts.
A passivation layer 78 is formed on an entire surface of the substrate 60 including the source electrodes 70a and 70b and the drain electrodes 72a and 72b, and exposes the drain electrode 72b of the synchronization adjusting TFT Tc. A pixel electrode 80 is formed on the passivation layer 78 and is connected to the exposed drain electrode 72b. 
In the above structure, the aperture ratio is reduced because the connection line 74 for connecting the driving TFT Ts and the synchronization adjusting TFT Tc still occupies a part of the aperture area.
Thus, in each of the related art substrates above, the pixel electrodes do not cover substantially all of the pixel regions. Although not drawn to scale, between about 5-10% of the aperture area is lost due to the connection line being formed in the pixel region.
A vertical electric field mode LCD device is described in the first and second embodiments of the related art, and an in-plane switching (IPS) mode LCD device will be explained hereinafter with reference to FIGS. 8 to 10.
The IPS mode LCD device has a wider viewing angle than the vertical electric field mode LCD device of the first and second embodiments. However, since a common electrode and a pixel electrode are formed in one pixel, the IPS mode LCD device has a reduced aperture ratio.
FIG. 8 is a plan view showing an array substrate for an IPS mode LCD device of the related art.
As shown in FIG. 8, gate lines 94 are formed on a substrate 90 in a first direction and a data line 110 is formed in a second direction. The gate lines 94 and the data line 110 perpendicularly cross each other to define a first pixel region P1 and a second pixel region P2. A common line 96 is formed parallel to the gate lines 94, and traverses the first and second pixel regions P1 and P2.
A driving TFT Ts is formed in each pixel region P1 and P2 and a synchronization adjusting TFT Tc is formed in the first pixel region P1. The synchronization adjusting TFT Tc can be formed in one of the two pixel regions (the odd pixel region and the even pixel region, above) adjoining each other with respect to a single data line 110.
Pixel electrodes 114a and 114b are formed in the pixel regions P1 and P2, respectively. The pixel electrode 114a of the first pixel region P1 is connected to the synchronization adjusting TFT Tc and the pixel electrode 114b of the second pixel region P2 is connected to the driving TFT Ts. The pixel electrodes 114a and 114b are parallel to the data line 110. Additionally, a common electrode 98 is formed in each pixel region P1 and P2. The common electrode 98 includes a plurality of patterns, which are parallel to the pixel electrodes 114a and 114b and alternate with the pixel electrodes 114a and 114b in respective pixel regions P1 and P2.
A storage capacitor Cst is formed over the common line 96 in each pixel region P1 and P2. A part of the common line 96 functions as a first electrode and an extension part DL extending from each pixel electrode 114a and 114b acts as a second electrode of the storage capacitor Cst.
The adjacent pixel regions P1 and P2, left and right in the context of the figure, receive signals from the same data line 110. To sequentially transmit the signals, the synchronization adjusting TFT Tc is formed in one of the pixel regions P1 and P2 as stated above.
Therefore, a connection line 112 is formed in the first pixel region P1 to connect a drain electrode 108a of the driving TFT Ts with a source electrode 106b of the synchronization adjusting TFT Tc, and the aperture ratio is accordingly decreased.
FIGS. 9 and 10 show cross-sections of an array substrate for an IPS mode LCD device of the related art. FIG. 9 is a cross-sectional view along the line IX-IX of FIG. 8 and FIG. 10 is a cross-sectional view along the line X-X of FIG. 8.
As shown in FIGS. 9 and 10, pixel regions P1 and P2 are defined on a substrate 90. A synchronization adjusting TFT Tc is formed in one of the pixel regions P1 and P2, for example, in the pixel region P1.
More particularly, a gate electrode 92a for the driving TFT Ts and a gate electrode 92b for the synchronization adjusting TFT Tc are formed on the substrate 90. Although not shown in the figures, gate lines, a common line 96 and common electrodes 98 are formed of the same material in the same layer as the gate electrodes 92a and 92b. The gate lines are spaced apart from each other, and are connected to the gate electrodes 92a and 92b, respectively. The common line 96 is parallel to and spaced apart from the gate lines. As shown in FIG.8, the common electrodes 98 vertically extend from the common line 96.
A gate insulating layer 100 is formed on the gate electrodes 92a and 92b, and active layers 102a and 102b and ohmic contact layers 104a and 104b are sequentially formed on the gate insulating layer 100 over the gate electrodes 92a and 92b. 
Source electrodes 106a and 106b and drain electrodes 108a and 108b are formed on the ohmic contact layers 104a and 104b. The source electrodes 106a and 106b are spaced apart from the drain electrodes 108a and 108b, respectively. A data line 110 and a connection line 112 are formed of the same material in the same layer as the source electrodes 106a and 106b and the drain electrodes 108a and 108b. The data line 110 is connected to the source electrodes 106a and 106b and the connection line 112 is connected to the drain electrode 108a of the driving TFT Ts and the source electrode 106b of the synchronization adjusting TFT Tc in the pixel region P1.
Meanwhile, pixel electrodes 114a and 114b are formed in the pixel regions P1 and P2. Although not shown in FIGS. 9 and 10, the pixel electrode 114a of the pixel region P1 is connected to the synchronization adjusting TFT Tc and the pixel electrode 114b of the pixel region P2 is connected to the driving TFT Ts. The pixel electrodes 114a and 114b are parallel to and alternate the common electrodes 98.
However, as stated above, the connection line 112 is formed in the pixel region P1, thereby reducing the aperture ratio of the device.